Anode Sensing Circuit For Single Photon Avalanche Diodes Patent Application (2025)

U.S. patent application number 16/718762 was filed with the patent office on 2021-06-24 for anode sensing circuit for single photon avalanche diodes. This patent application is currently assigned to STMicroelectronics (Research & Development) Limited. The applicant listed for this patent is STMicroelectronics (Research & Development) Limited. Invention is credited to Mohammed AL-RAWHANI, Neale DUTTON, Elisa LACOMBE, John Kevin MOORE, Bruce RAE.

ANODE SENSING CIRCUIT FOR SINGLE PHOTON AVALANCHE DIODES

Abstract

A pixel includes a single photon avalanche diode (SPAD) having acathode coupled to a high voltage supply through a quenchingelement, with the SPAD having a capacitance at its anode formedfrom a deep trench isolation, with the quenching element having asufficiently high resistance such that the capacitance is not fullycharged when the SPAD is struck by an incoming photon. The pixelincludes a clamp transistor configured to be controlled by avoltage clamp control signal to clamp voltage at an anode of theSPAD when the SPAD is struck by an incoming photon to be no morethan a threshold clamped anode voltage, and readout circuitrycoupled to receive the clamped anode voltage from the clamptransistor and to generate a pixel output therefrom. The thresholdclamped anode voltage is below a maximum operating voltage ratingof transistors forming the readout circuitry.

Claims

1. An array of single photon avalanche diodes (SPADs), comprising:a plurality of pixels, each pixel comprising: a SPAD; a transistorcircuit coupled configured to quench an anode voltage of the SPADwhen the SPAD is struck by an incoming photon and to clamp theanode voltage to be no more than a threshold clamped anode voltage;readout circuitry coupled to receive the clamped anode voltage fromthe transistor circuit and to generate a pixel output therefrom,wherein the threshold clamped anode voltage is below a maximumvoltage rating of transistors forming the readout circuitry; and aregulation circuit configured to generate a control signal for thetransistor circuits of the plurality of pixels.

2. The array of claim 1, wherein the transistor circuit comprises ahigh voltage transistor configured to clamp the anode voltage basedupon the control signal.

3. The array of claim 2, wherein the transistor circuit furthercomprises a quenching element in series with the high voltagetransistor.

4. The array of claim 3, wherein the quenching element comprises afirst low voltage transistor.

5. The array of claim 3, wherein the transistor circuit furthercomprises a second low voltage transistor coupled to the highvoltage transistor and configured to selectively disable thepixel.

6. The array of claim 1, wherein the regulation circuit comprises alow dropout amplifier (LDO) that forces the control signal to beequal to a clamped voltage reference signal.

7. A circuit, comprising: at least one pixel comprising: a singlephoton avalanche diode (SPAD) having a cathode coupled to a highvoltage supply node, and an anode; a first n-channel transistorhaving a drain coupled to the anode of the SPAD, a source coupledto a clamped anode voltage output node, and a gate coupled to avoltage clamp control signal; a second n-channel transistor havinga drain coupled to the clamped anode voltage output node, a source,and a gate coupled to a quenching voltage control signal; a thirdn-channel transistor having a drain coupled to the source of thesecond n-channel transistor, a source coupled to ground, and a gatecoupled to an enable signal; wherein the voltage clamp controlsignal and the quenching voltage control signal are set so as toquench an anode voltage of the SPAD when the SPAD is struck by aphoton and clamp the anode voltage to be no more than a thresholdclamped anode voltage, wherein the threshold clamped anode voltageis below a maximum operating voltage rating of the second and thirdn-channel transistors.

8. The circuit of claim 7, wherein the first n-channel transistoris a high-voltage transistor, and wherein the second and thirdn-channel transistors are low-voltage transistors capable ofwithstanding less voltage than the first n-channel transistor.

9. The circuit of claim 8, wherein the first n-channel transistoris an extended drain transistor; and wherein the second and thirdn-channel transistors are single layer gate oxide transistors.

10. The circuit of claim 9, further comprising an inverter havingan input coupled to the clamped anode voltage output node and anoutput providing an output signal, the inverter being formed fromsingle layer gate oxide transistors.

11. The circuit of claim 7, wherein the at least one pixelcomprises an array of pixels; and further comprising a regulationcircuit generating the voltage clamp control signal for each pixelof the array of pixels.

12. The circuit of claim 11, wherein the regulation circuitcomprises a low dropout amplifier that forces the voltage clampcontrol signal to be equal to a clamped voltage referencesignal.

13. The circuit of claim 11, wherein the regulation circuitcomprises: a first n-channel transistor having a drain coupled to asupply voltage, a source, and a gate biased by a cascode controlsignal; a second n-channel transistor having a drain coupled to thesource of the first n-channel transistor of the regulation circuit,a source, and a gate; a third n-channel transistor having a draincoupled to the source of the second n-channel transistor of theregulation circuit, a source, and a gate coupled to the quenchingvoltage control signal; a fourth n-channel transistor having adrain coupled to the source of the third n-channel transistor ofthe regulation circuit, a source coupled to ground, and a gatecoupled to the supply voltage; and an amplifier having anon-inverting terminal coupled to a clamped voltage referencesignal, a non-inverting terminal coupled to the source of thesecond n-channel transistor of the regulation circuit, and anoutput coupled to a gate of the second n-channel transistor of theregulation circuit.

14. The circuit of claim 13, wherein the second n-channeltransistor of the regulation circuit is an extended drain n-channeltransistor.

15. A circuit, comprising: at least one pixel comprising: a singlephoton avalanche diode (SPAD) having a cathode coupled to a highvoltage supply through a quenching element, wherein the SPAD has acapacitance at its anode formed from a deep trench isolation,wherein the quenching element has a sufficiently high resistancesuch that the capacitance is not fully charged when the SPAD isstruck by an incoming photon; a clamp transistor configured to becontrolled by a voltage clamp control signal to clamp voltage at ananode of the SPAD when the SPAD is struck by an incoming photon tobe no more than a threshold clamped anode voltage; and readoutcircuitry coupled to receive the clamped anode voltage from theclamp transistor and to generate a pixel output therefrom, whereinthe threshold clamped anode voltage is below a maximum operatingvoltage rating of transistors forming the readout circuitry.

16. The circuit of claim 15, wherein the readout circuitrycomprises an inverter having an input coupled to receive theclamped anode voltage from the clamp transistor.

17. The circuit of claim 15, further comprising an enabletransistor coupled between the clamp transistor and ground, theenable transistor configured to selectively enable the circuit.

18. The circuit of claim 17, wherein the enable transistorcomprises a double layer gate oxide (GO2) n-channel transistor.

19. The circuit of claim 15, wherein the clamp transistor comprisesa high voltage n-channel transistor and wherein the transistorsforming the readout circuitry are low voltage transistors.

20. The circuit of claim 15, wherein the clamp transistor comprisesan extended drain double layer gate oxide (GO2) n-channeltransistor.

21. The circuit of claim 15, wherein the clamp transistor comprisesan extended drain double layer gate oxide (GO2) n-channeltransistor; further comprising an enable transistor coupled toground and a biasing transistor coupled between the clamptransistor and the enable transistor; wherein the enable transistorcomprises a single layer gate oxide (GO1) n-channel transistor;wherein the biasing transistor comprises a single layer gate oxide(GO1) n-channel transistor; and wherein the transistors forming thereadout circuitry are low voltage transistors.

22. The circuit of claim 21, wherein the at least one pixelcomprises an array of pixels; and further comprising a regulationcircuit generating the voltage clamp control signal for each pixelof the array of pixels.

23. The circuit of claim 22, wherein the regulation circuitcomprises a low dropout amplifier that forces the voltage clampcontrol signal to be equal to a clamped voltage referencesignal.

24. The circuit of claim 22, wherein the regulation circuitcomprises: a first n-channel transistor having a drain coupled to asupply voltage, a source, and a gate biased by a cascode controlsignal; a second n-channel transistor having a drain coupled to thesource of the first n-channel transistor of the regulation circuit,a source, and a gate; a third n-channel transistor having a draincoupled to the source of the second n-channel transistor of theregulation circuit, a source, and a gate coupled to a bias signal;a fourth n-channel transistor having a drain coupled to the sourceof the third n-channel transistor of the regulation circuit, asource coupled to ground, and a gate coupled to the supply voltage;and an amplifier having a non-inverting terminal coupled to aclamped voltage reference signal, a non-inverting terminal coupledto the source of the second n-channel transistor of the regulationcircuit, and an output coupled to a gate of the second n-channeltransistor of the regulation circuit.

25. The circuit of claim 24, wherein the second n-channeltransistor of the regulation circuit is an extended drain n-channeltransistor.

26. The circuit of claim 15, wherein the clamp transistor comprisesan extended drain double layer gate oxide (GO2) n-channeltransistor; further comprising an enable transistor coupled betweenthe clamp transistor and ground; and wherein the enable transistorcomprises a single layer gate oxide (GO1) n-channel transistor.

27. The circuit of claim 26, wherein the at least one pixelcomprises an array of pixels; and further comprising a regulationcircuit generating the voltage clamp control signal for each pixelof the array of pixels.

28. The circuit of claim 27, wherein the regulation circuitcomprises a low dropout amplifier that forces the voltage clampcontrol signal to be equal to a clamped voltage referencesignal.

29. The circuit of claim 27, wherein the regulation circuitcomprises: a first n-channel transistor having a drain coupled to asupply voltage, a source, and a gate biased by a cascode controlsignal; a second n-channel transistor having a drain coupled to thesource of the first n-channel transistor of the regulation circuit,a source, and a gate; a third n-channel transistor having a draincoupled to the source of the second n-channel transistor of theregulation circuit, a source, and a gate coupled to a bias signal;a fourth n-channel transistor having a drain coupled to the sourceof the third n-channel transistor of the regulation circuit, asource coupled to ground, and a gate coupled to the supply voltage;and an amplifier having a non-inverting terminal coupled to aclamped voltage reference signal, a non-inverting terminal coupledto the source of the second n-channel transistor of the regulationcircuit, and an output coupled to a gate of the second n-channeltransistor of the regulation circuit.

30. The circuit of claim 29, wherein the second n-channeltransistor of the regulation circuit is an extended drain n-channeltransistor.

31. A method of operating a pixel, the method comprising: quenchinga single photon avalanche diode (SPAD) from its cathodesufficiently such that a capacitance at its anode from a deeptrench isolation does not fully charge when the SPAD is struck byan incoming photon; clamping a voltage at an anode of the SPAD whenthe SPAD is struck by an incoming photon to be no more than athreshold clamped anode voltage; and reading the clamped anodevoltage using readout circuitry having a maximum operating voltagerating of less than the threshold clamped anode voltage.

32. The method of claim 31, wherein the voltage at the anode of theSPAD is clamped using an n-channel extended drain double layer gateoxide transistor.

33. The method of claim 32, further comprising selectively enablingthe pixel using an n-channel double layer gate oxide enabletransistor coupled between the extended drain double layer gateoxide transistor and ground.

Description

TECHNICAL FIELD

[0001] This application is directed to clamping circuits for singlephoton avalanche diodes (SPADs) that utilize low voltage controland provide for low voltage readout.

BACKGROUND

[0002] Single photon avalanche diode (SPAD) photodetectors arebased on a PN junction that is reverse biased at a voltageexceeding a breakdown voltage. When a photon-generated carrier (viathe internal photoelectric effect) is injected into the depletionregion of the PN junction, a self-sustaining avalanche ensues, anddetection of current output as a result of this avalanche can beused to indicate detection of the photon that generated thecarrier.

[0003] There are challenges involved in the detection of thisavalanche current, since the current pulses can produce a highvoltage. This means that circuits are to be implemented to convertthis high voltage resulting from the avalanche to a low voltagedomain suitable for reading and control using sub 100 nm lowvoltage CMOS technology, so that SPAD based photodetection arrayscan be utilized in time of flight ranging applications.

[0004] In general, it is desired for each SPAD pixel (whichincludes the SPAD itself as well as its associated readout andcontrol circuitry) to be small in size so as to be able to providea greater resolution per given size of a SPAD based photodetectionarray. Therefore, the smaller the size of the readout and controlcircuitry for each SPAD pixel, the smaller the size of each SPADpixel, and consequently the greater the resolution per given sizeof a SPAD based photodetection array incorporating these SPADpixels.

[0005] A sample prior art SPAD pixel 10 is shown in FIG. 1. Thepixel 10 includes a SPAD D1 having its cathode coupled to a highvoltage supply VHV through a quench resistance Rq and its anodecoupled to the drain of an n-channel transistor T1. Transistor T1in turn has its source coupled to the drain of an n-channeltransistor T2, which has its drain coupled to ground. Transistor T1is biased by a first control signal Ctrl1, which has a fixedvoltage, while transistor T2 is biased by an alternating controlsignal Ctr12.

[0006] When Ctr12 goes high, it turns on, connecting the anode ofthe SPAD D1 to ground, setting the reverse bias voltage of the SPADD1 above the breakdown voltage, while the clamp diode D2disconnects the anode of the SPAD D1 from the VSPADOFF voltage.When an incoming photon strikes the SPAD D1, its cathode voltagewill swing between the high voltage and a lower voltage, creating acurrent pulse that is detected by the detection module 11. Theavalanche is quenched by the quench resistance Rq, resetting theSPAD D1 for the next detection. The purpose for Ctrl1 being a fixedvoltage is to bias the transistor T1 so that it limits the currentinrush to transistor T2 during the avalanche, protecting T2 fromdamage.

[0007] However, the use of the capacitor Cc, may consume anundesirable amount of area depending on the technology in which itis formed (e.g., CMOS). In addition, the capacitance value of thecapacitor Cc is dependent on process and temperature, meaning thatin an array of such SPAD pixels 10, the different SPADs may exhibitdifferent responses, reducing the accuracy of results. Stillfurther, the SPAD D1, due to the use of the detection module 11 atthe cathode of D1, is larger than desired, further consuming anundesirable amount of area.

[0008] In an attempt to enable the formation of smaller pixels thanthe SPAD pixels 10, the above referenced drawbacks need addressing.Therefore, further development into this area is required.

SUMMARY

[0009] Disclosed herein is an array of single photon avalanchediodes (SPADs) including a plurality of pixels. Each pixelincludes, at least: a SPAD; a transistor circuit coupled configuredto quench an anode voltage of the SPAD when the SPAD is struck byan incoming photon and to clamp the anode voltage to be no morethan a threshold clamped anode voltage; readout circuitry coupledto receive the clamped anode voltage from the transistor circuitand to generate a pixel output therefrom, wherein the thresholdclamped anode voltage is below a maximum voltage rating oftransistors forming the readout circuitry; and a regulation circuitconfigured to generate a control signal for the transistor circuitsof the plurality of pixels.

[0010] The transistor circuit may include a high voltage transistorconfigured to clamp the anode voltage based upon the controlsignal.

[0011] The transistor circuit may further include a quenchingelement in series with the high voltage transistor.

[0012] The quenching element may further include a first lowvoltage transistor.

[0013] The transistor circuit may further include a second lowvoltage transistor coupled to the high voltage transistor andconfigured to selectively disable the pixel.

[0014] The regulation circuit may include a low dropout amplifier(LDO) that forces the control signal to be equal to a clampedvoltage reference signal.

[0015] Also disclosed herein is a circuit including at least onepixel. The at least one pixel may include, at least: a singlephoton avalanche diode (SPAD) having a cathode coupled to a highvoltage supply node, and an anode; a first n-channel transistorhaving a drain coupled to the anode of the SPAD, a source coupledto a clamped anode voltage output node, and a gate coupled to avoltage clamp control signal; a second n-channel transistor havinga drain coupled to the clamped anode voltage output node, a source,and a gate coupled to a quenching voltage control signal; and athird n-channel transistor having a drain coupled to the source ofthe second n-channel transistor, a source coupled to ground, and agate coupled to an enable signal; wherein the voltage clamp controlsignal and the quenching voltage control signal are set so as toquench an anode voltage of the SPAD when the SPAD is struck by aphoton and clamp the anode voltage to be no more than a thresholdclamped anode voltage, wherein the threshold clamped anode voltageis below a maximum operating voltage rating of the second and thirdn-channel transistors.

[0016] The first n-channel transistor may be a high-voltagetransistor, and the second and third n-channel transistors may below-voltage transistors capable of withstanding less voltage thanthe first n-channel transistor.

[0017] The first n-channel transistor may be an extended draintransistor, and the second and third n-channel transistors may besingle layer gate oxide transistors.

[0018] An inverter may have an input coupled to the clamped anodevoltage output node and an output providing an output signal, theinverter being formed from single layer gate oxide transistors.

[0019] The at least one pixel may include an array of pixels, aregulation circuit may generate the voltage clamp control signalfor each pixel of the array of pixels.

[0020] The regulation circuit may include a low dropout amplifierthat forces the voltage clamp control signal to be equal to aclamped voltage reference signal.

[0021] The regulation circuit may include: a first n-channeltransistor having a drain coupled to a supply voltage, a source,and a gate biased by a cascode control signal; a second n-channeltransistor having a drain coupled to the source of the firstn-channel transistor of the regulation circuit, a source, and agate; a third n-channel transistor having a drain coupled to thesource of the second n-channel transistor of the regulationcircuit, a source, and a gate coupled to the quenching voltagecontrol signal; a fourth n-channel transistor having a draincoupled to the source of the third n-channel transistor of theregulation circuit, a source coupled to ground, and a gate coupledto the supply voltage; and an amplifier having a non-invertingterminal coupled to a clamped voltage reference signal, anon-inverting terminal coupled to the source of the secondn-channel transistor of the regulation circuit, and an outputcoupled to a gate of the second n-channel transistor of theregulation circuit.

[0022] The second n-channel transistor of the regulation circuitmay be an extended drain n-channel transistor.

[0023] Also disclosed herein is a circuit including at least onepixel. The at least one pixel may include: a single photonavalanche diode (SPAD) having a cathode coupled to a high voltagesupply through a quenching element, wherein the SPAD has acapacitance at its anode formed from a deep trench isolation,wherein the quenching element has a sufficiently high resistancesuch that the capacitance is not fully charged when the SPAD isstruck by an incoming photon; a clamp transistor configured to becontrolled by a voltage clamp control signal to clamp voltage at ananode of the SPAD when the SPAD is struck by an incoming photon tobe no more than a threshold clamped anode voltage; and readoutcircuitry coupled to receive the clamped anode voltage from theclamp transistor and to generate a pixel output therefrom, whereinthe threshold clamped anode voltage is below a maximum operatingvoltage rating of transistors forming the readout circuitry.

[0024] The readout circuitry may be an inverter having an inputcoupled to receive the clamped anode voltage from the clamptransistor.

[0025] An enable transistor may be coupled between the clamptransistor and ground, the enable transistor configured toselectively enable the circuit.

[0026] The enable transistor may be a double layer gate oxide (GO2)n-channel transistor. The clamp transistor may be a high voltagen-channel transistor and the transistors forming the readoutcircuitry may be low voltage transistors.

[0027] The clamp transistor may be an extended drain double layergate oxide (GO2) n-channel transistor.

[0028] The clamp transistor may be an extended drain double layergate oxide (GO2) n-channel transistor. An enable transistor may becoupled to ground and a biasing transistor may be coupled betweenthe clamp transistor and the enable transistor. The enabletransistor may be a single layer gate oxide (GO1) n-channeltransistor. The biasing transistor may be a single layer gate oxide(GO1) n-channel transistor. The transistors forming the readoutcircuitry may be low voltage transistors.

[0029] The at least one pixel may be an array of pixels, and aregulation circuit may generate the voltage clamp control signalfor each pixel of the array of pixels.

[0030] The regulation circuit may be a low dropout amplifier thatforces the voltage clamp control signal to be equal to a clampedvoltage reference signal.

[0031] The regulation circuit may include, at least: a firstn-channel transistor having a drain coupled to a supply voltage, asource, and a gate biased by a cascode control signal; a secondn-channel transistor having a drain coupled to the source of thefirst n-channel transistor of the regulation circuit, a source, anda gate; a third n-channel transistor having a drain coupled to thesource of the second n-channel transistor of the regulationcircuit, a source, and a gate coupled to a bias signal; a fourthn-channel transistor having a drain coupled to the source of thethird n-channel transistor of the regulation circuit, a sourcecoupled to ground, and a gate coupled to the supply voltage; and anamplifier having a non-inverting terminal coupled to a clampedvoltage reference signal, a non-inverting terminal coupled to thesource of the second n-channel transistor of the regulationcircuit, and an output coupled to a gate of the second n-channeltransistor of the regulation circuit.

[0032] The second n-channel transistor of the regulation circuitmay be an extended drain n-channel transistor.

[0033] The clamp transistor may be an extended drain double layergate oxide (GO2) n-channel transistor. An enable transistor may becoupled between the clamp transistor and ground. The enabletransistor may be a single layer gate oxide (GO1) n-channeltransistor.

[0034] The at least one pixel may be an array of pixels. Aregulation circuit may generate the voltage clamp control signalfor each pixel of the array of pixels.

[0035] The regulation circuit may be a low dropout amplifier thatforces the voltage clamp control signal to be equal to a clampedvoltage reference signal.

[0036] The regulation circuit may include, at least: a firstn-channel transistor having a drain coupled to a supply voltage, asource, and a gate biased by a cascode control signal; a secondn-channel transistor having a drain coupled to the source of thefirst n-channel transistor of the regulation circuit, a source, anda gate; a third n-channel transistor having a drain coupled to thesource of the second n-channel transistor of the regulationcircuit, a source, and a gate coupled to a bias signal; a fourthn-channel transistor having a drain coupled to the source of thethird n-channel transistor of the regulation circuit, a sourcecoupled to ground, and a gate coupled to the supply voltage; and anamplifier having a non-inverting terminal coupled to a clampedvoltage reference signal, a non-inverting terminal coupled to thesource of the second n-channel transistor of the regulationcircuit, and an output coupled to a gate of the second n-channeltransistor of the regulation circuit.

[0037] The second n-channel transistor of the regulation circuitmay be an extended drain n-channel transistor.

[0038] Also disclosed herein is a method of operating a pixel. Themethod may include, at least: quenching a single photon avalanchediode (SPAD) from its cathode sufficiently such that a capacitanceat its anode from a deep trench isolation does not fully chargewhen the SPAD is struck by an incoming photon; clamping a voltageat an anode of the SPAD when the SPAD is struck by an incomingphoton to be no more than a threshold clamped anode voltage; andreading the clamped anode voltage using readout circuitry having amaximum operating voltage rating of less than the threshold clampedanode voltage.

[0039] The voltage at the anode of the SPAD may be clamped using ann-channel extended drain double layer gate oxide transistor.

[0040] The method may include selectively enabling the pixel usingan n-channel double layer gate oxide enable transistor coupledbetween the extended drain double layer gate oxide transistor andground.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG. 1 is a schematic diagram of a prior art SPAD basedsensing pixel.

[0042] FIG. 2 is a schematic diagram of a first embodiment of SPADbased sensing pixel disclosed herein.

[0043] FIG. 3 is a series of graphs of the pixel of FIG. 2 inoperation showing anode voltage over time, clamped anode voltageover time, and output voltage over time.

[0044] FIG. 4 is a schematic diagram showing the Vclamp regulationcircuit used to provide the Vclamp voltage to the pixel of FIG.2.

[0045] FIG. 5 is a schematic diagram of a second embodiment of SPADbased sensing pixel disclosed herein.

[0046] FIG. 5A is a series of graphs of the pixel of FIG.5 inoperation showing cathode voltage over time, anode voltage overtime, and clamped anode voltage over time.

[0047] FIG. 5B is a series of graphs of the pixel of FIG.5 inoperation (if the quenching element Rq were removed) showingcathode voltage over time, anode voltage over time, and clampedanode voltage over time.

[0048] FIG. 6 is a schematic diagram of a third embodiment of aSPAD based sensing pixel and its associated Vclamp regulationcircuit.

[0049] FIG. 7 is a schematic diagram of a fourth embodiment of aSPAD based sensing pixel and its associated Vclamp regulationcircuit.

DETAILED DESCRIPTION

[0050] The following disclosure enables a person skilled in the artto make and use the subject matter disclosed herein. The generalprinciples described herein may be applied to embodiments andapplications other than those detailed above without departing fromthe spirit and scope of this disclosure. This disclosure is notintended to be limited to the embodiments shown, but is to beaccorded the widest scope consistent with the principles andfeatures disclosed or suggested herein.

[0051] To address the above drawbacks, a variety of SPAD basedsensing pixels have been developed. A first embodiment is nowdescribed with reference to FIG. 2.

[0052] In FIG. 2, the pixel 20 includes a SPAD D1 having itscathode coupled to a high voltage supply VHV and its anode coupledto the drain of n-channel extended drain transistor Tr1. TransistorTr1 has its source coupled to the drain of n-channel thin (e.g.,single layer) gate oxide (GO1) transistor Tr2, and its gate biasedby the Vclamp signal. Transistor Tr2 has its source coupled to thedrain of n-channel single layer gate oxide (GO1) transistor Tr3 andits gate biased by the Vquench signal. Transistor Tr3 has itssource coupled to voltage reference AVSS, and its gate controlledby the En GO1 signal. The En GO1 signal (which is the enable signalfor the pixel 20) is generated by in-pixel GO1 memory/enable logic21. A clamp diode D2 has its cathode coupled to a VSPADOFF voltageand its anode coupled to the anode of the SPAD D1. The voltage atthe drain of transistor Tr2 is, as will be explained, the clampedanode voltage of the SPAD D1, and passed through an inverter 22also implemented in GO1 technology to provide the output signalOUT.

[0053] In operation, transistors Tr1 and Tr2, as biased by Vclampand Vquench, have a resistance similar to that of the quenchingelement Rq present at the cathode of the SPAD Sp of the prior artdesign of FIG. 1. When an incoming photon strikes the SPAD D1, theanode swing will be between 0 and an excess voltage Vex of about 5V, as seen in the anode voltage graph of FIG. 3. The n-channelextended drain transistor Trl is capable of withstanding highervoltages (e.g., 7 V), so the swing at the anode of the SPAD D1 doesnot present an issue to transistor Tr1. Using transistor Tr1 as aclamping element, for example by biasing its gate with a Vclamp of2.5 V, the voltage at the source (the clamped anode voltage) willbe in the range of 1.1 V or less, as seen in the clamped anodevoltage graph of FIG. 3, enabling the use of the low voltage GO1transistors Tr2 and Tr3, which can tolerate no more than about 1.2V.

[0054] By changing the value of Vquench, the drain to sourceresistance of Tr2 changes, and therefore the quench resistance seenby the anode of the SPAD D1 will change, and thus the pulse deadtime will change. By changing the value of Vclamp, the clampedanode voltage can be changed. Note that even when the anode voltageis clamped to around 0.55 V, the GO1 based inverter 22 is stillable to trigger, as can be seen in the output voltage graph of FIG.3.

[0055] Since Tr2 is a low voltage GO1 transistor, this pixel 20 hasthe advantage of being able to use a low voltage GO1 transistor Tr3for enabling the pixel 20. Note that GO1 type transistors consume asmall amount of area, and that the use of discrete resistors andcapacitors are also eliminated, so this pixel design saves areaover prior art pixel designs.

[0056] Note that the pixel 20 design described above is for asingle pixel within an array of pixels. As seen in FIG. 4, aregulation circuit 30 generates Vclamp for the array of pixels(meaning that the regulation circuit 30 generates a single value ofVclamp that is passed to each pixel within the array ofpixels).

[0057] The regulation circuit 30 is comprised of n-channeltransistor Tc1 having its drain coupled to the power supply VDD,its source coupled to the drain of extended drain n-channeltransistor Tc2, and its gate biased by the Vcas signal. Then-channel transistor Tc2 has its source coupled to the drain ofn-channel transistor Tc3 and its gate coupled to the output ofamplifier 31. The n-channel transistor Tc3 has its source coupledto the drain of n-channel transistor Tr4 and its gate biased by theVquench signal (which may or may not be the same Vquench signal asreceived by the transistors Tr2 of the pixels 20). The n-channeltransistor Tr4 has its source coupled to AVSS and its gate tied toVDD to maintain Tr4 in an on-state. Note that the source oftransistor Tc2 is coupled to the inverting terminal of theamplifier 31, and that the amplifier 31 receives a clamped voltagereference at its non-inverting terminal, essentially forming a lowdropout (LDO) amplifier that operates to have Vclamp match theclamped voltage reference input to the amplifier 31.

[0058] A second embodiment is now described with reference to FIGS.5, 5A, and 5B.

[0059] In FIG. 5, the pixel 40 includes a top tier chip 41 and abottom tier chip 42; this is a stacked die solution where the topdie includes the circuitry in box 41 and the bottom die includesthe circuitry in box 42. The top tier chip 41 is now described andincludes a SPAD D1 having its cathode coupled to a high voltagesupply VHV through a quenching resistance Rq and its anode coupledto ground through a deep trench isolation parasitic capacitanceCdti that results from the fact that the SPAD D1 is formed usingthree dimensional SPAD technology in which different SPADs areseparated from one another by deep trench isolations. A clamp diodeD2 has its cathode coupled to a VSPADOFF voltage and its anodecoupled to the anode of the SPAD Dl.

[0060] The bottom tier chip 42 is now described and includes ann-channel extended drain double layer gate oxide (GO2) transistorMN1 having its drain coupled to the anode of the SPAD D1.Transistor MN1 has its source coupled to the drain of n-channeldouble layer gate oxide (GO2) transistor MN2, and its gate biasedby the Vcas signal. Transistor MN2 has its source coupled to groundand its gate biased by the Enable signal (which is the enablesignal for the pixel 40, and is generated by an in-pixel GO2memory/enable logic which is not shown in FIG. 5 for simplicity).The input to an inverter INV is coupled to the drain of MN1 and theoutput OUT is of the pixel 40 is provided at the output of theinverter INV. The inverter INV is comprised of low voltagep-channel transistor MP1 having its drain coupled to a supplyvoltage VDD, its source coupled to the output OUT, and its gatecoupled to the gate of low voltage n-channel transistor MN3. Lowvoltage n-channel transistor MN3 has its drain coupled to theoutput OUT, its source coupled to ground, and its gate coupled tothe gate of the p-channel transistor MP1.

[0061] In operation, when an incoming photon strikes the SPAD D1,the large quenching resistance Rq quickly quenches the currentthrough the SPAD D1 without having to charge any parasiticcapacitor element at the cathode, so that the cathode voltage ofthe SPAD D1 quickly falls from VHV to VHV less an excess voltageVex before recharging, as can be seen in FIG. 5A. This quickquenching process during avalanche means that the current throughthe SPAD D1 is low and only sufficient to slowly charge thecapacitance Cdti to a level (i.e. 2 V) where it is able to triggerthe inverter INV without the need to fully charge the Cdticapacitor to Vex (i.e 5V), as also seen in FIG. 5A.

[0062] The extended drain n-channel transistor MN1, properly biasedby the Vcas signal, clamps the anode voltage to below 1.1 V, asseen in FIG. 5A, enabling the use of low voltage transistors MP1and MN3 in the inverter INV for readout.

[0063] Without the quenching element Rq, the cathode voltage of theSPAD D1 would remain high during avalanche, meaning that theparasitic capacitance Cdti would be charged to Vex, increasingpower consumption, as can be seen in FIG. 5B.

[0064] This embodiment combines the advantages of cathode-sidequenching and anode-side reading, which reduces power consumption.This embodiment also removes the use of discrete capacitors, savingarea over prior art pixel designs.

[0065] A third embodiment is now described with reference to FIG.6.

[0066] In FIG. 6, the pixel 50 includes a top tier chip 51 and abottom tier chip 52. The top tier chip 51 is now described andincludes a SPAD D1 having its cathode coupled to a high voltagesupply VHV through a quenching resistance Rq and its anode coupledto ground through a parasitic deep trench isolation capacitanceCdti that results from the fact that the SPAD D1 is formed usingthree dimensional SPAD technology in which different SPADs areseparated from one another by deep trench isolations. A clamp diodeD2 has its cathode coupled to a VSPADOFF voltage and its anodecoupled to the anode of the SPAD D1.

[0067] The bottom tier chip 52 is now described and includes anextended drain double layer gate oxide (GO2) n-channel transistorTr1 having its source coupled to the drain of n-channel singlelayer gate oxide (GO1) transistor Tr2, and its gate biased by theVclamp signal. Transistor Tr2 has its source coupled to the drainof n-channel single layer gate oxide (GO1) transistor Tr3 and itsgate biased by the Vbias signal. Transistor Tr3 has its sourcecoupled to voltage reference AVSS, and its gate controlled by theEn_GO1 signal. The En_GO1 signal (which is the enable signal forthe pixel 50) is generated by in-pixel GO1 memory/enable logic 53.The voltage at the drain of transistor Tr2 is, as will beexplained, the clamped anode voltage of the SPAD D1, and passedthrough an inverter 54 also implemented in GO1 technology toprovide the output signal OUT.

[0068] In operation, when an incoming photon strikes the SPAD D1,the large quenching resistance Rq quickly quenches the currentthrough the SPAD D1 without having to charge any parasiticcapacitor element at the cathode, so that the cathode voltage ofthe SPAD D1 quickly falls from VHV to VHV less an excess voltageVex before recharging. This quick quenching process duringavalanche means that the current through the SPAD D1 is low andonly sufficient to slowly charge the parasitic capacitance Cdti toa level (i.e 2 V) where it is able to trigger the inverter INVwithout the need to fully charge the Cdti capacitor to Vex (i.e5V).

[0069] Notice that as opposed to the first embodiment in which thetransistors Tr1 and Tr2 perform quenching, here the quenching isperformed at the cathode by the quenching element Rq. Therefore,here, transistor Tr1 serves to clamp the anode voltage of the SPADD1 to a safe level for GO1 transistors forming the inverter 54,under control of the Vclamp signal. The resistance seen by theanode of the SPAD D1 can be tuned by adjusting the Vbias signal,allowing for fine tuning of the clamped anode voltage.

[0070] This embodiment combines the advantages of cathode-sidequenching and anode-side reading, which reduces power consumption.This embodiment also removes the use of discrete capacitors, savingarea over prior art pixel designs. In addition, since Tr2 is a lowvoltage GO1 transistor, this pixel 50 has the advantage of beingable to use a low voltage GO1 transistor Tr3 for enabling the pixel50, providing for further area savings.

[0071] Note that the pixel 50 design described above is for asingle pixel within an array of pixels. The regulation circuit 60generates Vclamp for the array of pixels (meaning that theregulation circuit 60 generates a single value of Vclamp that ispassed to each pixel within the array of pixels).

[0072] The regulation circuit 60 is comprised of n-channeltransistor Tc1 having its drain coupled to the power supply VDD,its source coupled to the drain of extended drain n-channeltransistor Tc2, and its gate biased by the Vcas signal. Then-channel transistor Tc2 has its source coupled to the drain ofn-channel transistor Tc3 and its gate coupled to the output ofamplifier 61. The n-channel transistor Tc3 has its source coupledto the drain of n-channel transistor Tr4 and its gate biased by theVbias signal (which may or may not be the same Vbias signal asreceived by the transistors Tr2 of the pixels 20). The n-channeltransistor Tr4 has its source coupled to AVSS and its gate tied toVDD to maintain Tr4 in an on-state. Note that the source oftransistor Tc2 is coupled to the inverting terminal of theamplifier 61, and that the amplifier 61 receives a clamped voltagereference at its non-inverting terminal, essentially forming a lowdropout (LDO) amplifier that operates to have Vclamp match theclamped voltage reference input to the amplifier 61.

[0073] A fourth embodiment is now described with reference to FIG.7. The fourth embodiment is a variant of the third embodiment wherethe bottom tier chip 52' of the pixel 50' lacks transistor Tr2.Instead, the source of the transistor Tr1 is coupled to the drainof transistor Tr3. Otherwise, the fourth embodiment and thirdembodiment are sufficiently similar that additional descriptionneed not be given for sake of brevity, although do note that byremoving transistor Tr2, the fourth embodiment lacks the precisetunability of the clamped anode voltage at the third embodimentprovides.

[0074] While the disclosure has been described with respect to alimited number of embodiments, those skilled in the art, havingbenefit of this disclosure, will appreciate that other embodimentscan be envisioned that do not depart from the scope of thedisclosure as disclosed herein. Accordingly, the scope of thedisclosure shall be limited only by the attached claims.

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